1. Field of the Invention
This invention generally relates to a method and apparatus for improving reference voltage stability in semiconductor devices. More specifically, the invention involves the integration of a circuit using a voltage reference to generate a constant voltage with a semiconductor device to actively drive a reference voltage in the device.
2. State of the Art
Semiconductor devices such as logic chips, processors, and memory devices commonly employ at least one voltage reference signal (“VREF”) for testing and operation. Use of a VREF signal in semiconductor devices is well known in the art. Problems associated with VREF stability caused by variances in a VREF source or noise on the semiconductor device are also well known. For example, a reference voltage generating circuit incorporated into a memory device (e.g., DRAM, SDRAM, or flash memory) generates VREF from a power supply voltage supplied to the memory device. Variations in the power supply voltage are translated to variations in VREF. These variations may cause the memory device to operate defectively. Likewise, noise from other signals on the memory device may also cause variations in the generated VREF resulting in similar operational defects.
In other memory devices, such as Rambus and double data rate (DDR) memory, a VREF signal is bused to the device rather than being generated on the device. The bused VREF is subject to the same noise and signal variations as a VREF generated on the device. This results in an equal propensity for operational defects due to VREF fluctuations.
The use of a VREF signal with a semiconductor device is best explained with reference to an example. FIG. 5 is a simplified block diagram illustrating the workings of a memory device 500 such as an SDRAM as known in the art. The memory device 500 includes an address register 510, row address controls 520, column address controls 530, at least one memory array 540, data input/output controls 550, control logic 560 and a VREF generator 570. An external power supply provides a power supply voltage VDD to the memory device 500. To reduce the number of terminals on the memory device, a reference voltage (VREF) is created from the power supply voltage VDD rather than from a power supply independent of that producing VDD. VDD is introduced to the VREF generator 570 which generates a VREF signal having a desired voltage. For example, the VREF generator 570 may be a voltage divider which produces VREF having half of the voltage of VDD. The generated VREF signal is routed to both the address register 510 and the data input/output controls 550 where it is used in the operation of the memory device 500.
A simplistic generalization of VREF operation in a memory device demonstrates some of the problems associated with varying VREF signals. The VREF signal generated from VDD by the VREF generator 570 has a voltage which is approximately half of the power supply voltage VDD applied to the memory device 500. A signal, such as an address signal corresponding to a memory cell location in the memory array 540, received by the memory device 500 at the address register 510, is compared to VREF. If the signal has a voltage which is higher than VREF, then the signal is high and corresponds to a logical value of one. If the signal has a voltage lower than VREF, then the signal is low, having a logical value of zero. In this manner, received signals may be compared to VREF and assigned values which define memory locations within the memory array 540. Similarly, data read from or written to the memory device 500 is compared to VREF to establish whether each data bit is high or low.
Because VREF is usually generated from the power supply voltage VDD, variances in the power supply voltage VDD cause fluctuations in VREF. If the variance is great enough to drive VREF closer to the power supply voltage VDD, a signal received by the memory device 500 which normally would have been defined as high may, instead, be mischaracterized as low. The altered characterization of the signal results in a malfunction of the memory device 500. Similarly, noise created by other circuits and power supplies on the memory device may also cause variances in VDD which in turn cause variances in VREF resulting in the mischaracterization of signals received by the memory device.
To reduce the problems associated with VREF variations in semiconductor devices, integrated circuits and memory devices, numerous VREF regulation circuits have been devised to aid in stabilizing VREF. These circuits may be separate from, or coincidental with, the VREF generation circuits for the integrated circuits. One example of a circuit designed to compensate for variation in VREF involves the addition of decoupling capacitors between the power rails of an integrated circuit. The capacitors help eliminate stray capacitance, thereby reducing the amount of noise within the memory device. Similarly, resistive decoupling of noisy nodes within a memory device eliminates noise at the noisy node but enhances noise elsewhere in the circuit. Likewise, diodes are used to reduce the amount of noise in such circuits. Other examples of stabilized VREF generation circuits are described in U.S. Pat. Nos. 5,212,440 and 4,477,736, the disclosures of each of which are hereby incorporated herein by reference. However, these circuits do not eliminate all of the noise in VREF.
Although a number of VREF regulation circuits have been described and used with memory devices and other semiconductor devices, problems caused by noise within the device and by fluctuations in power supplies remain. Furthermore, these problems seem to be accentuated in high speed memory devices and other semiconductor devices operating at ever lower voltages. Therefore, it is desirous to provide a VREF to a semiconductor device which is not as susceptible to power supply fluctuations or noise from the circuits in the semiconductor device.